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AEGIS Platform Architecture: Tamper-Resistant Computing
AEGIS Platform Architecture: Tamper-Resistant Computing
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AEGIS Platform Architecture: Tamper-Resistant Computing
Edward Suh briefly describes the architecture of the AEGIS secure processor and its key primitives, namely, physical nonclone-able functions and memory integrity verification. Researchers at MIT have built a tamper-resistant platform using a single-chip secure processor called AEGIS. The platform protects applications from physical attacks as well as software attacks, enabling several applications such as secure sensor networks, certified execution, and copy protection of media and software. From the Series:CSE Colloquia - 2005
Channel: ResearchChannel
Category: Technology
Video Length: 3061
Date Found: February 12, 2009
Date Produced: March 29, 2005
View Count: 2
 
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